The present invention relates to synchronous buck converters and more particularly to improving the efficiency of synchronous buck converters in the discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operations.
As illustrated in FIG. 1, a synchronous buck converter 10 includes a switching stage 12 having high (control)- and low-side (synchronous) switches S1 and S2, e.g., MOSFETs, series connected at a switching node A across a DC supply B+. An inductor L is connected between the switching node and an output filter capacitor C across which is coupled a load R. The high- and low-side switches S1 and S2 include gate terminals, which are controlled by a gate driver 14 and are switched complementarily.
The buck converter operates in CCM if the current through the inductor L does not fall to zero during the switching cycle. The buck converter operates in DCM where the load energy requirement is light.
The switching ON time in the converter is determined by a ramp slope. In commonly used synchronous buck converters, the switching ON time is the same in both DCM and CCM. When a synchronous buck converter is in DCM, the higher slew rate of the ramp will require higher cycle switching frequency than necessary to support the load. However, the higher cycle switching frequency presents larger power losses due to the high switching rate. What is needed is an adjustment to the slope of the ramp when the synchronous buck converter is in DCM.